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Core Configuration
Table 4-8. Bus Control Register (BCR) Bit Definitions (Continued)
Bit
Number
12–10
Bit Name
BA2W[2–0]
Reset Value
111
Bus Area 2 Wait State Control
Description
(7 wait states) Defines the number of wait states (1–7) inserted into each external SRAM access
to Area 2 (DRAM accesses are not affected by these bits). Area 2 is the area
defined by AAR2.
Note:
Do not program the value of these bits as zero, since SRAM memory
access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. This trailing wait state increases the data hold
time and the memory release time and does not increase the memory access time.
9–5
BA1W[4–0]
11111
(31 wait
states)
Bus Area 1 Wait State Control
Defines the number of wait states (1–31) inserted into each external SRAM access
to Area 1 (DRAM accesses are not affected by these bits). Area 1 is the area
defined by AAR1.
Note:
Do not program the value of these bits as zero, since SRAM memory
access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. When selecting eight or more wait states, two
additional wait states are inserted at the end of the access. These trailing wait
states increase the data hold time and the memory release time and do not
increase the memory access time.
4–0
BA0W[4–0]
11111
(31 wait
states)
Bus Area 0 Wait State Control
Defines the number of wait states (1–31) inserted in each external SRAM access
to Area 0 (DRAM accesses are not affected by these bits). Area 0 is the area
defined by AAR0.
Note:
Do not program the value of these bits as zero, since SRAM memory
access requires at least one wait state.
When selecting four through seven wait states, one additional wait state is inserted
at the end of the access. When selecting eight or more wait states, two additional
wait states are inserted at the end of the access. These trailing wait states increase
the data hold time and the memory release time and do not increase the memory
access time.
4.6.2
DRAM Control Register (DCR)
The DRAM controller is an efficient interface to dynamic RAM devices in both random
read/write cycles and Fast Access mode (Page mode). An on-chip DRAM controller controls the
page hit circuit, the address multiplexing (row address and column address), the control signal
generation ( CAS and RAS ) and the refresh access generation ( CAS before RAS ) for a variety of
DRAM module sizes and access times. The on-chip DRAM controller configuration is
determined by the DRAM Control Register (DCR). The DRAM Control Register (DCR) is a
24-bit read/write register that controls and configures the external DRAM accesses. The DCR
bits are shown in Figure 4-7 .
DSP56311 User’s Manual, Rev. 2
4-22
Freescale Semiconductor
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